Draw the pipeline chart and calculate CPI of the loop with the following machine settings for different static scheduling algorithms: -Integer ALU instructions take 1 cycle to execute - LOAD instructions require 1 cycle to calculate the effective address and 1 more cycle to read the value from the memory (Assume a perfect cache with no cache misses) -MUL instructions require 2 cycles to execute (i.e. 2 stages of execution) in a non-pipelined multiplication unit. -Assume a full-bypass circuitry is present in the architecture. - Assume simple control hazard resolution is implemented (i.e. stalling the pipeline for 2 cycles). Apply software pipelining to the original loop. What is the difference in CPI of 100 iterations of the original and of the software pipelined version of the loop