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The general representation of the student ID is 1C2Y2X2C1Y1X1, so, if your student ID is 1220520 , then X,Y, and C values for the three test cases as follow: Note: If any value from the set /C3,X2X1,C2,Y1,X11 is X or 9 , vou need to replace it by 1 f) (10 points) Write a single behavioral Verilog module that models the designed ALU. g) (5 points) Generate the waveforms of the behavioral ALU defined in Part (i), assumes that X and Y are 4-bits and their values based on your student ID should be set as follows: The general representation of the student ID is 1C2Y2X2C1Y1X1, so, if your student ID is 1220520 , then X. Y. and C values for the three test cases as follow: Note: If any value from the set iC31Y33X2C3Y12X1 is x or y2 vou need to replace it by 1 Instructions: 1. This project is to be done individually. 2. This project should be implemented in Verilog HDL using Quartus software. 3. Snapshots should be clear and should contain the date and the time of your computer. 4. Captions should be added to your figures and tables. Also, you are required to explain and describe these figures and tables in your project. 5. Comments are required to be added in your Verilog codes. Submission: You are required to submit a compressed file (.zip file) and it should contain: a. Project folder, name it by "Project_ID" (if your ID is 1220520, then the folder name should be "Project_1220520"). This folder should contain all modules files (i.e. Verilog files and Waveforms), name your modules/waveforms by moduleName ID and waveformName ID (e.g. if your module is Adder and your ID is 1191020 , then the name of the module should be "Adder_1220520"). b. Report in pdf format (only pdf format), name it by "Report_ID" (if your ID is 1220520, then the folder name should be "Report_1220520". This report should contain your answers for all parts with detailed explanation and supported by snapshotvfigures, commands, designs, runs, tables, etc. The general representation of the student ID is 1C2Y2X2C1Y1X1, so, if your student ID is 1220520 , then X,Y, and C values for the three test cases as follows: Note: If any value trom me set iCis XiXiC1X1,X11s8 or y2 vou need to replace it by 1 f) (10 points) Write a single behavioral Verilog module that models the designed ALU, g) (5 points) Generate the waveforms of the behavioral ALU defined in Part (5), assumes that X and Y are 4-bits and their values based on your student ID should be set as follows: The general representation of the student ID is 1C2Y2X2C1Y1X1, so, if your student ID is 1220520 , then X,Y, and C values for the three test eases as follows: Note: If any value from the set /C2X2X2Ci2X42X1 is XorY2 you need to replace it by 1 Instructions: 1. This project is to be done individually. 2. This project should be implemented in Verilog HDL using Quartus software. 3. Snapshots should be clear and should contain the date and the time of your computer. 4. Captions should be added to your figures and tables. Also, you are required to explain and describe these figures and tables in your project. 5. Comments are required to be added in your Verilog codes. Submission: You are required to submit a compressed file (zip file) and it should contain: a. Project folder, name it by "Project_ID" (if your ID is 1220520, then the folder name should be "Project_1220520"). This folder should contain all modules files (i.e. Verilog files and Waveforms), name your modules/waveforms by moduleName_ID and waveformName ID (e.g. if your module is Adder and your ID is 1191020, then the name of the module should be "Adder_1220520"). b. Report in pdf format (only pdf format), name it by "Report_ID" (if your ID is 1220520, then the folder name should be "Report_1220520". This report should contain your answers for all parts with detailed explanation and supported by snapshots figures, commands, designs, runs, tables, ete