e) (10 pts) Implement the datapath in Verilog. Include the RTL Netlist from Quartus.

Problem 2 (80 pts) Design an application-specific processor that computes the average of 16 unsigned 4-bit values stored in consecutive addresses in a ROM. The processor should have the following ports: input clk, input reset, input [3:0] din, output [3:0] addr, output [3:0] avg // data from ROM // ROM address /1 integer average (don't worry about remainder) The processor should use an approach that iteratively calculates the sum of the number in the ROM. When it reaches the last address, it should get the average by dividing the sum by 16. Note that because you are taking the sum o 16 4-bit numbers, your internal register that holds the sum will need to be wider that 4 bits (how wide does it need to be?). In performing the division by 16, take advantage of the fact that division by 2 can be done by simply shifting the number by n bits to the right, or truncating the n least-significant bits. Problem 2 (80 pts) Design an application-specific processor that computes the average of 16 unsigned 4-bit values stored in consecutive addresses in a ROM. The processor should have the following ports: input clk, input reset, input [3:0] din, output [3:0] addr, output [3:0] avg // data from ROM // ROM address /1 integer average (don't worry about remainder) The processor should use an approach that iteratively calculates the sum of the number in the ROM. When it reaches the last address, it should get the average by dividing the sum by 16. Note that because you are taking the sum o 16 4-bit numbers, your internal register that holds the sum will need to be wider that 4 bits (how wide does it need to be?). In performing the division by 16, take advantage of the fact that division by 2 can be done by simply shifting the number by n bits to the right, or truncating the n least-significant bits