e following datapath with an Arithmetic Logic Unit an eight-register nsi register file organized around a single bus. The ALU is to apply add, subtract, and so on operations to its two input operands to generate an output result. The register file has ain asynchronous read and a synchronous write. That is, as soon as the Read Enable (RE) is asserted, the register file selects the indicated 32-bit register and presents its value on the Data Out (DO). On the other hand, the Write Enable (WE) is sampled only on the rising edge of the clock, and only writes the indicated register from the Data In (DI ines on the same edge that WE is asserted. The ALU and Register File share the Bus via a 32-bit wide 2:1 multiplexer. When SelALU is set to 1, the ALU path is connected to the Bus. Otherwise, the Register File path is connected to the Bus. The datapath must support three-address instructions of the form Rz f Rx Ry. To make use of a single bus architecture, the ALU can be surrounded by one, two, or three 32-bit temporary registers, labeled A, B, and C, as shown below (the temporary registers are shown as dotted lines - the correct solution requires at least one and possibly all three of the registers) Note that 32-bit temporary registers are positive edge triggered devices: they store their inputs at their outputs on the rising edge of the clock signal when the corresponding load register signal (LdA, LdB, or LdC) is asserted. You are asked to use the fewest of the temporary registers and possible clock cycles to facilitate the execution of the three-address instruction using this datapath. Determine the registers and the minimum solution and demonstrate it using a timing diagram for essential signals. For each clock cycle needed indicate the control signals that must be asserted to implement the register transfers for the three-address instructions. number of clock cycles to accomplish t his design modification task. Detail your SelALUAs Mux DI DO RegRd RegRdsel 'RE RegWr RReg[2:0] Reg WE File Clk DI Clk ALU Out Clk DO LdB Clk e following datapath with an Arithmetic Logic Unit an eight-register nsi register file organized around a single bus. The ALU is to apply add, subtract, and so on operations to its two input operands to generate an output result. The register file has ain asynchronous read and a synchronous write. That is, as soon as the Read Enable (RE) is asserted, the register file selects the indicated 32-bit register and presents its value on the Data Out (DO). On the other hand, the Write Enable (WE) is sampled only on the rising edge of the clock, and only writes the indicated register from the Data In (DI ines on the same edge that WE is asserted. The ALU and Register File share the Bus via a 32-bit wide 2:1 multiplexer. When SelALU is set to 1, the ALU path is connected to the Bus. Otherwise, the Register File path is connected to the Bus. The datapath must support three-address instructions of the form Rz f Rx Ry. To make use of a single bus architecture, the ALU can be surrounded by one, two, or three 32-bit temporary registers, labeled A, B, and C, as shown below (the temporary registers are shown as dotted lines - the correct solution requires at least one and possibly all three of the registers) Note that 32-bit temporary registers are positive edge triggered devices: they store their inputs at their outputs on the rising edge of the clock signal when the corresponding load register signal (LdA, LdB, or LdC) is asserted. You are asked to use the fewest of the temporary registers and possible clock cycles to facilitate the execution of the three-address instruction using this datapath. Determine the registers and the minimum solution and demonstrate it using a timing diagram for essential signals. For each clock cycle needed indicate the control signals that must be asserted to implement the register transfers for the three-address instructions. number of clock cycles to accomplish t his design modification task. Detail your SelALUAs Mux DI DO RegRd RegRdsel 'RE RegWr RReg[2:0] Reg WE File Clk DI Clk ALU Out Clk DO LdB Clk