E5.1

5.1 Consider the circuit shown in Figure E5.1. Show the design is that of a 1- b it full adder by forming the truth tables and equations of the circuit.

5.3 Compute C6 of the carry- lookahead generator equations.

5.4 Using the delays of gates as given in question 5.2, find the delay for each of the carry equations C 1 , C 2 , C 3 , C 4 , C 5 , and C 6 of a ripple carry adder. Assume the operands are A = A 5 A 4 A 3 A 2 A 1 A 0 and B = B 5 B 4 B 3 B 2 B 1 B 0 . Generalize your answer to compute the delay for Cn. Write your answer in terms of n.

5.6 Show the design of a 2- bit magnitude comparator from 1- bit magnitude comparators.

5.8 An n- bit magnitude comparator can be designed from 1- bit magnitude comparators with enable lines. Show the design of a 5- bit magnitude comparator from 1- bit magnitude comparators with enable lines. Hint the design can be accomplished with five 1- bit comparators and 2 additional gates.

AB Ci