Each pipeline stage in Figure

$4\mathrm{.}33$

$$has some latency. Additionally, pipelining

introduces registers between stages

$($

Figure

$4\mathrm{.}35$

$)$

$,$

$$and each of these adds an

additional latency. The remaining problems in this exercise assume the following

latencies for logic within each pipeline stage and for each register between two

stages:

$4\mathrm{.}17$

$.$

$4$

$[$

$5$

$]$

$<$

$4$

$.$

$6$

$>$

$$Assuming there are no stalls, what is the speed

$-$

up achieved by

pipelining a single

$-$

cycle datapath?