ECE228 Spring 2018 aunz Multiple Choice Questions I. Netlist is a representation of a circuit. a. graphic b. text-based C. handwritten d. pictoria 1. Verilog is case sensitive. rue b. False gital loge i. Verilog language used for simulation and synthesis of digital a. True b. False V. "beginmodule" and "endmodule" are both reserved words in Verilog a. True b. False V. If x=4"b1100 then x