EEE$205$

Laboratory $5$

ALU Design

In this experiment you need to build an $8-$bit Arithmetic Logic Unit $($ALU$)$ in Quartus Prime

design suite. ALU is a critical design element in computer architecture.

Design specifications:

There will be two $8-$bit input operands: A and B$.$

There will be a mode select input $($mod$\_$sel$)$ where:

When mod$\_$sel $=0,$ there will be arithmetic operations.

When mod$\_$sel $=1,$ there will be logic operations.

Secondly, there will be operation selection op$\_$sel input where:

In arithmetic mode $($when mod$\_$sel $=0)$:

op$\_$sel $=0,$ addition

op$\_$sel $=1,$ subtraction

op$\_$sel $=2$ multiplication

op$\_$sel $=3,$ output is $-A$

In arithmetic mode $($when mod $\_$sel $=0)$:

op$\_$sel $=1,$ Out $=$ A $||$ B $($bitwise OR operation$)$

op$\_$sel $=2,$ Out $=A^{{?}^{{?}^{?}}}B($bitwise OR operation$)$

op$\_$sel $=3,$ Out $=A^{\text{'}}($inverse of A input$)$

your general code structure should be similar to:

module ALU$\_8$bit$($A$,$ B$,$ Out, mod$\_$sel, op$\_$sel$)$;

$//$here comes input output pin and bitsize definitions

reg $[7$:$0]$ Out;

always @$(*)$

begin

if sel $=0)$

begin

case $($op$\_$sel$)$

$0$ : Out $=$dots.

$1$: Out $=$dots

$2$: Out $=$dots $3$: Out $=$dots

default: Out $=$dots

endcase

end

else if $($mod$\_$sel$==1)$

begin

case$($op$\_$sel$)$

$0$: Out $=$dots

$1$: Out $=$dots

$2$: Out $=$dots

$3$: Out $=$dots

default: Out $=$dots

endcase

end

end

endmodule

Questions:

$1-$ What is the bit size for the output of $88$ multiplication?

$2-$ What types of optimizations can be made for the ALU here?

$3-$ What is the advantage of the always keywords in the code? Could we design the ALU

in another way, explain.