EENG INFE 115 Logic Design Lab Final 09 January, 2021 Start Time: 15:30 Submission Deadline: 21:30 (Cyprus Time) Question: 4 bit Full Adder Construct a 4 bit full adder as presented in Figure 1. Generate a truth table for the output. In report, you should post a screenshot of your circuit and truth table. The hints for construction are given in the note below. B3 A3 B2 31 ca Full Adder Full Adder Full Adder Full Adder CB 54 Figure 1.4 Bit Full Adder NOTE: M is made selector (Use Toggle Switch and keep it zero) Al-A4 and B1-B4 are input switches (Use Toggle Switches) SI-S4 are sum outputs (Use Light Bulb) A single full adder circuit is given below in Figure 2. You will make 4 full adder circuit and cascade them such as the Carry Output (Cout) of one Full adder is the Carry Input (Cin) of next Full adder sw, sw, T Figure 2. A single Full Adder You are supposed to construct FIGURE 1. I just provided figure 2 for you to remember what a full-adder You will use logic.ly for constructing the circuit. The guide to access logic.ly is given on next page. Guide for Logic.by Step ONE: Open kisic.ly Step TWO: Click on Free Trial Step THREE: Click on try Logkly in your browser L You may also try lady is your own Step FOUR: Drag the components from the menu ce left and drop on the work area on et WORK AREA Components 8 Ingkan