ELEC3651 HW VirtualMemory (Compatibility Mode]-Word (Product Activation REF MAILINGS REVIEW VIEW Problew Assume the following: 32-bit addresses (virtual and physical) 1 KB Page size 4 KB, 2-way set-associative, write through cache, LRU replacement (the cache holds 4 KB total of data, do not count other fields in this count) 64 Byte cache block (line) size 4-entry fully associative TLB A Number of bits needed to specify byte offset in a cache line: B. Number of bits needed to specify the tag: C. Number of bits needed to specify the index: D. Total number of blocks (lines) in the cache: Problem 4 Given the cache described in the previous problem (problem 3) and the following C code (assume ints are 4 bytes): idefine MAX 2048 int A[MAX] 1 Assume A starts at address ox1000 sum sum + ALE); Answer the following questions. Ignore variables and sum for this question (focus only on array A). Assume no context switches. Assume the two loops run in the order shown above You may give answers as fractions or percentages. If you do not have enough information to answer the question, say "Not Enough Info A. What is the hit rate for the cache in the first loop B. what is the hit rate for the cache in the second loop: C. What is the hit rate for the TLB in the first loop: D. Number of page faults in the second loop