Element Search $(15\%)$

In this assignment you are requested to design a HLSM for a digital system that receives an array of ten $7-$bit unsigned numbers $($i$.$e$.$ A$[6$:$0][0$:$9])$ and finds the location of the first element before which all the elements are smaller than it$,$ and after which all are greater. The output location is $4-$bit and will be between $0$ and $9$ when an element is found. However, if no such element is found, then the output location is set to $15.$

For example, if the array contents are: $\{14,9,23,18,43,49,45,60,100,90\}$ then there are two elements that satisfy the search criteria $($i$.$e$.A[4]=43$ and $A[7]=60).$ Since the system is supposed to return the location of the first element that satisfies the search criteria then the output location should be $4.$ Another example, if the array contents are: $\{14,9,23,18,43,49,45,60,100,43\}$ then none of the elements satisfies the search criteria and the output location should be $15.$

The following block diagram shows the inputs and outputs of vour svstem:

At "Reset", the system should asynchronously proceed to an INITIAL state and wait for the "Start" signal to become active.

In the INITIAL state, the input array $"$A$"$ must be stored in an internal array "Ain" such that Ain$[0]=A[0],$Ain$[1]=A[1],$ and so on$.$

Once the "Start" signal is active, the system proceeds to traverse the values within "Ain" to find the first element that satisfies the search critieria.

After the search is complete, the system proceeds to the DONE state and remains until the "Ack" signal becomes active, at which time the system returns back to the INITIAL state.

You should design and test two versions of this system as described by the submission details below.

Here is what you need to submit:

Moore$\_$Search$\_$ID$1\_$ID$2\_$ID$3.$v: This Verilog file should include your RTL design of the system implemented as a Moore machine. Your control unit $($CU$)$ and data path unit $($DPU$)$ must be implemented using a single always procedural block. Notice that the file name must include the students' IDs.

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Mealy$\_$Search$\_$ID$1\_$ID$2\_$ID$3.$v: This Verilog file should include your RTL design of the system implemented as a Mealy machine. Your control unit $($CU$)$ and data path unit $($DPU$)$ must be implemented using a single always procedural block. Notice that the file name must include the students' IDs.

Search$\_$tb$.$v: This Verilog file should serve as a testbench that instantiates the two versions of the system, initializes the array and passes it as input to the two instants. The test bench should print the total number of clock cycles $($ignoring the cycles spent in the INITIAL and DONE states$)$ and the output location for the two versions.

Testing Hints:

When testing and evaluating your designs, you should try the worst$-$case scenario $($i$.$e$.$ the element at location $9$ is the only element that satisfies the search criteria$),$ the best$-$case scenario $($i$.$e$.$ the element at location $0$ satisfies the search criteria$),$ and any other corner cases you can think of$.$

Submission Deadline

Monday January $1^{st}2024$@$11\mathrm{.}591$MOf $2$

You must submit your files threugh Microsoft Teans as a single compressed file.

Group size can be one, two, or three students and each group must submit one set of files.