En Adid ALU Owa PC Address Instruction Instruction memory Regler Register Regent Mom Address Dale memory Data Now Corte 31. Assuming that each component takes time as indicated in the below, what is the critical path (e.g., ALU-> Mux -> I-Mem) when the MIPS executes AND Rd, Rs, Rt" instruction? I-Mem 200ps, Add 70ps, Mux 20ps, ALU 90ps, Regs 90ps, D-Mem 250ps, Control 40ps. 32. How long does it take to complete the AND instruction? (Do not take the time for PC read/update into consideration.) 33. Assuming that each component takea time as indicated in the above, what is the critical path (e.g., ALU -> Mux -> I-Mem) when the MIPS executes LW Rt, Offs(Rs)" instruction? 34. How long does it take to complete the LW instruction? (Do not take the time for PC read/update into consideration.) 35. Critical paths for AND and LW takes different amount of time. However, CPU clock cycle must be fixed and is determined by the shortest critical path among those for all instructions. True or False? En Adid ALU Owa PC Address Instruction Instruction memory Regler Register Regent Mom Address Dale memory Data Now Corte 31. Assuming that each component takes time as indicated in the below, what is the critical path (e.g., ALU-> Mux -> I-Mem) when the MIPS executes AND Rd, Rs, Rt" instruction? I-Mem 200ps, Add 70ps, Mux 20ps, ALU 90ps, Regs 90ps, D-Mem 250ps, Control 40ps. 32. How long does it take to complete the AND instruction? (Do not take the time for PC read/update into consideration.) 33. Assuming that each component takea time as indicated in the above, what is the critical path (e.g., ALU -> Mux -> I-Mem) when the MIPS executes LW Rt, Offs(Rs)" instruction? 34. How long does it take to complete the LW instruction? (Do not take the time for PC read/update into consideration.) 35. Critical paths for AND and LW takes different amount of time. However, CPU clock cycle must be fixed and is determined by the shortest critical path among those for all instructions. True or False