Even if you can't answer everything Partial answers will do!

The MIPS R4000 processor has an eight-stage pipeline, with stages shown below IF IS RF EX DF DS TC WB Reg Data Memory Reg Memory 2A. Speedup What is the ideal pipeline speedup for this processor? 2B. Forwarding For data forwarding, how many additional inputs are needed for the multiplexers at the inputs to the ALU? Where does each come from? What kind of hazard(s) do these address? 2C. Branching options The branch delay is 3 cycles. Ir branches make 20% of the total instruction mix and 14% of the branches are taken, evaluate the effective CPI and adjusted pipelines speedup for each of these options a. Stall for three cycles b Expose one delay slot and stall for two wnen the delay slot can be filled 60% of the time and the resulting computation is useful 80% of the time C. Expose two delay slots and stall for one cycle where the first slot statistics are the same as (b), and the second slot is filled 10% of the time. with useful computation 40% of the time d. Expose one delay slot and predict not taken for the other two cycles (what was really done). 2D. Branches in practice Given the strategy in (d), which of the following instructions are executed when the branch is taken? Which are executed when the branch is not taken? BNEZ Ri, Target SUB Ri, R2, R3 ADD R1, R1, R4 Target: SU R3, R3, R1 ADD R2, R1, R4 ADD R2, R2, R3