Exercise 16.8 Fibonacci numbers, I. Draw the block diagram for a datapath circuit to compute 16-bit Fibonacci Numbers. During each cycle, the circuit should output the next Fibonacci number (starting with 0 after reset). The circuit should signal when the next number is larger than 16 bits. (15 points) Do not use a lookup table to solve this problem. This is sequential logic (chapter 14), not combinational logic. That means it can remember the previous Fibonacci number and do addition. Exercise 16.9 Fibonacci Numbers, II. Implement your datapath FSM from Exercise 16.8 in Verilog. (10 points) Turn in both the Verilog code and a copy of the Verilog output. Turn in Verilog files and text files, not screen captures or scans of hand-written answers