Exercise 5: (15 pts) Draw a logic diagram using registers and dedicated multiplexers to implement the following transfers among three registers: C1: R24 R1 C2: RO R1, R2 + RO C3: RO R2, R1 R2 Exercise 6: (15 pts) Using two binary counters and logic gates, construct a binary counter that counts from decimal 9 through decimal 199. Add an additional input and logic to the counter to initialize it synchronously to 9 when the signal IN1T is 1