Exercise Design a datapath that consists of four four-bit, general-purpose registers and one four-bit processor status word (PSW) register. There are four status bits, carry, overflow, sign, and zero; these will be stored in the four bits of the PSW. The PSW must be written for any operation that uses the function unit but not for those that do not. The function unit for the datapath is the same as designed in the previous lab. During a single clock cycle the register file will produce two outputs. A and B. It has the ability to write to a single register on the rising edge of the clock signal but is not required to write to any register. Output A of the register file is connected directly to the A bus that is the input to the function unit. Bus B data can come from the B output of the register file or from constant data that is supplied by the control unit. Bus B is the B input to the function unit. The data input to the register file is from bus D. Bus D receives data either from the output of the function unit or from an external source, such as memory. Provide the datapath control word for the functions specified for the function unit in the previous laboratory and for load and store operations. The load operation will specify the address to read on the A bus and the data will be presented for the D bus. The store operation will specify the address to write on the A bus and the data to be stored will be from the B output of the register file. Exercise Design a datapath that consists of four four-bit, general-purpose registers and one four-bit processor status word (PSW) register. There are four status bits, carry, overflow, sign, and zero; these will be stored in the four bits of the PSW. The PSW must be written for any operation that uses the function unit but not for those that do not. The function unit for the datapath is the same as designed in the previous lab. During a single clock cycle the register file will produce two outputs. A and B. It has the ability to write to a single register on the rising edge of the clock signal but is not required to write to any register. Output A of the register file is connected directly to the A bus that is the input to the function unit. Bus B data can come from the B output of the register file or from constant data that is supplied by the control unit. Bus B is the B input to the function unit. The data input to the register file is from bus D. Bus D receives data either from the output of the function unit or from an external source, such as memory. Provide the datapath control word for the functions specified for the function unit in the previous laboratory and for load and store operations. The load operation will specify the address to read on the A bus and the data will be presented for the D bus. The store operation will specify the address to write on the A bus and the data to be stored will be from the B output of the register file
