Exercise number $2$:

Design of a signed multiplier

Design a circuit that multiplies two signed$-$binary

numbers. The numbers $($including the sign bit$)$ are

three bits. Use the following strategy:

$$ The circuit should convert any negative operand to

its positive $(2$s complement$)$ version.

$$ Perform the unsigned binary multiplication like you can

see in the image.

$$ If necessary, convert $(2$s complement$)$ the product

Z to a negative number.

My problems with this exercise are more inclined towards how to implement the two's complement with logical gates, where I would have to place it and what type of gates I would use to decide if it should be converted to positive or not.