Experiment $1$ Part $1$ :

The following VHDL code for $1-$bit adder $($from lecture $1).$

$1-$ Create a new project $($fulladder$1)$

$2-$ Add VHD file to the project then copy or print the above code

$3-$ Compile your project

$4-$ Add a waveform file to simulate the full adder.

Part $2$: The following VHDL code for $4-$bit adder built from $1-$bit adder.

$--$ VHDL for a $4-$bit adder built from $1-$bit adders.

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity fulladder$4$ is

port $($x$,$y : in std$\_$logic$\_$vector$(3$ downto $0)$;

cin : in std$\_$logic;

sum : out std$\_$logic$\_$vector$(3$ downto $0)$;

cout : out std$\_$logic$)$;

end fulladder$4$; $...$

architecture prototype of fulladder$4$ is

component fulladder$1$

port $($a$,$b$,$c : in std$\_$logic;

s$,$z : out std$\_$logic$)$;

end component;

signal c$1,$ c$2,$ c$3$ : std$\_$logic; $--$ temporary signals needed in the

architecture.

begin

bit$0$: fulladder$1$

port map $($a$=>$x$(0),$b$=>$y$(0),$c$=>$ cin,s$=>$ sum$(0),$z$=>$ c$1)$;

bit$1$: fulladder$1$

port map $($a$=>$x$(1),$b$=>$y$(1),$c$=>$ c$1,$s$=>$ sum$(1),$z$=>$ c$2)$;

bit$2$: fulladder$1$

port map $($a$=>$x$(2),$b$=>$y$(2),$c$=>$ c$2,$s$=>$ sum$(2),$z$=>$ c$3)$;

bit$3$: fulladder$1$

port map $($a$=>$x$(3),$b$=>$y$(3),$c$=>$ c$3,$s$=>$ sum$(3),$z$=>$ cout$)$;

end prototype;

library ieee;

use ieee.std$\_$logic$\_1164.$all;

entity FullAdder$1$ is

port$($ a$,$b$,$c : in std$\_$logic;

s$,$z : out std$\_$logic$)$;

end FullAdder$1$;

architecture prototype of FullAdder$1$ is

begin

s $<=$ a xor b xor c; $--$ equation for s

z $<=($a and b$)$ or $($a and c$)$ or $($b and c$)$; $--$ equation for z

end prototype;

$1-$ Create a new folder to save the new project in it$.$ Let$$s name it $$fulladder$4)$

$2-$ Copy FullAdder$1.$vhd fle $($i prrt $1)$ pid psrte $($rt $($i rthe iew folder

$3-$ Open Quartus software and create a new project $($fulladder$4)$

$-$ add FullAdder$1.$vhd file to the project

$4-$ Add VHD file to the project then copy or print the code of fulladder$4$

$5-$ Add an output to the entity to detect the overflow.

$6-$ Compile your project

a$.$ Determine the propagation delay from computational report $->$ Timing

analyzer

$7-$ Add waveform file to simulate the $4$ bit full adder.

a$.$ Simulation $($Simulate the fulladdre$4$ for different values of x and y$)$

b$.$ Timing $($Simulate the fulladdre$4$ for fixed value of x and y$)$

$8-$ Check RTLview of your design

Part $3$

$1.$ Copy the folder of fulladder$4$ project

$2.$ Modify the new copy of the project to design $8$ bit full adder

$3.$ Compile your project

a$.$ Determine the propagation delay from computational report $->$ Timing

analyzer

$4-$ Add waveform file to simulate the $4$ bit full adder.

b$.$ Simulation $($Simulate the fulladdre$4$ for different values of x and y$)$

c$.$ Timing $($Simulate the fulladdre$4$ for fixed value of x and y$)$

$5-$ Check RTLview of your design

Part $4$

Add the necessary changes to the code to design $4-$bit adder subtractor

$-$ create a new project $($ let$$s call it adder$\_$sub$4)$

$-$ Add the vhd files $($fulladder$1$ and fulladder$4$ to the project$)$

$-$ Change the entity name in fulladder$4.$vhd file to adder$\_$sub$4$ then add the necessary

changes in the code