Explain the operation of your circuit t to 2, p, and ically four- aped 45. Implement the 2 4 binary decoder with an enable input, as shown in Figure 10.47. Draw a nonabbreviated diagram of your circuit. the AND and XOR gates of the half adders. *(b) What is the maximum t ta outnut? (c) Design minimized two- 46/(a) Draw the implementation of the full adder in Figure 10.51 showing