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Explaination how did you get the answer please ? ? In the circuit shown below, two 8 - bit shift register are put in shift
Explaination how did you get the answer please In the circuit shown below, two bit shift register are put in shift right mode. Assume initially that:
RegARegB Flip flop is set ie
After applying clock cycles the decimal equivalent of RegA content as an bit signed s complement data is:
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