figure 4.24

Suppose the components in figure 4.24 have the following latencies (delays) Register (PC): 20 ps Adder: 100 ps I-Mem: 400 ps Control (including ALU control): 120 ps Register file: 200 ps Mux: 30 ps ALU: 120 ps D-Mem: 400 ps And: 10 ps Sing_extend: 5 ps Shift-left-2: 5 ps Ignore the setup time of registers and delays on wires Find out the minimum cycle time if only one of the following instructions is supported (without removing any components in the figure) Add LW: SW BE