Figure C$.18$ The implementation of the RISC V data path allows every instruction to be executed in $4$ or $5$ clock

cycles. Although the PC is shown in the portion of the data path that is used in instruction fetch and the registers are

shown in the portion of the data path that is used in instruction decode$/$register fetch, both of these functional units

are read as well as written by an instruction. Although we show these functional units in the cycle corresponding to

where they are read, the PC is written during the memory access clock cycle and the registers are written during the

write$-$back clock cycle. In both cases, the writes in later pipe stages are indicated by the multiplexer output $($in mem$-$

ory access or write$-$back$),$ which carries a value back to the PC or registers. These backward$-$flowing signals introduce

much of the complexity of pipelining, because they indicate the possibility of hazards.