Figure Q3 shows the characteristics of a hypothetical machine, relevant portions of memory, processor registers and some I/O devices. For the instruction format shown in Figure Q3(i), if it is an I/O instruction, bits 4 to 15 identifies a particular I/O device, else a memory address.

a) How many memory locations can this processor address? (b) This hypothetical machine is to execute the following program: 1. Load AC from device 4. 2. Add contents of memory location 880. 3. Store AC to memory location 881. There are three fetch and three execute cycles. The process can be divided into six steps or cycles. For each step or cycle, demonstrate what happens and list the contents of the following registers: (i) PC at the start of each cycle, (ii) AC at the end of each cycle and (iii) IR at the end of each cycle. Assume the initial values are as given in Figure Q3(v). Summarise your answer using the format given in Table Q3. Step

Step	PC at start of cycle	AC at end of cycle	IR at end of cycle
1 Fetch	?	?	?
	Description
2 Execute	?	?	?
	Description
...	...	...	....

Bit o 3 4 Opcode Memory address or I/O device number (1) Instruction format Bit 01 sign Magnitude (11) Integer format Program counter (PC) = Address of instruction Accumulator (AC) - Temporary storage Instruction register (IR)= Instruction being executed (iii) Internal CPU registers 0010 Store AC to memory 0011 = Load AC from I/O 0101 = Add to AC from memory (iv) Partial list of opcodes 500 501 Memory 3004 5880 2881 CPU registers 500 PC AC IR 502 880 0007 I/O Devices 881 0005 Dev 4 (All numbers are in hexadecimal) (v) Contents of memory, registers and I/O devices at start of program