Fill in the architecture to compute Y = AB + BC 1 library IEEE; 2 use IEEE.std_logic_1164.all; 3 entity abc is port( 4 5 6 7 8 9 10 ); 11 end abc; 12 13 architecture synth of abc is 14 begin 15 16 end; 17 18 a : in std_logic; b : in std_logic; c in std_logic; y out std_logic Your code here Rollback to previous