final answer

ID Q1 Assume that the individual stages of MIPS datapath have the following latencies: Your answer should be as the following format: 20s, 10ms, 20ns, 20ps ... and so on. No spaces in between and the letters are case-sensitive). LIF EX MEM WE 150ps 150ps 100ps 150ps 150ps What is the execution time of one (add instruction) for single cycle architecture