Find the truth table for the below figure for four clock cycles.

Mealy FSM Serial Adder (Section 8.5.1) Implement circuit: Note these are the same logical expressions as those for a full-adder (FA). b So, we can implement the FSM with a full- Full adder D adder. q 00 01 11 10 q oo 01 11 10 Module 79 carry-out Clock Reset Adder Shift register Shi ft register Y = ab + ay + by Clo ck David O. Johnson EECS 140/141 Q Shl ft register sum - A+B