FIRST ACTIVITY (100/100) PROBLEM: BCD Addition of two numbers. The operands (A and B) are 4-bit numbers represented in BCD (where only numbers from 0 to 9 are allowed). The result S is also represented in BCD. There is also a BCD carry out (cout). If any of the operands is greater than 9, the result S is invalid Example: 78-15. Here, cout 1, and S 0101 5. CMP Z(2) Z(3) otto A+B94 This circuit can be built out of two 4-bit binary a few logic gates as depicted in the figure adders and BCD Adder Operation: If A B>9S 6+2, cout - 1. Here, by adding 6, we "correct" the binary sum to make it look as BCD code. If A + B 9 SZ, cout 0 cout The figure below depicts the internal architecture of the 4-bit binary adder. The full adder circuit is also shown. FA FA FA FA E cout NEXYS A7-50T: Create a new Vivado Project. Select FULL ADDER the XC7A50T-1CSG324 Artix- Write the VHDL code for the BCD Adder. Use the 7 FPGA device. Structural Description: Create a separate file for the Full Adder, the 4-bit adder, the 'CMP' block, and the top file (BCD Adder). Write the VHDL testbench to test the circuit for the following cases: cout FA cout A#0x6, A=0x5, A#0x3, A=0x9, B=0x7, B=0x6, B=0x6, B=0x1 , cin-1 cin=1 cin=0 cin=0 cout=1, cout=1, cout=0, cout=1, S-0100 S-0010 S=1001 S-0000