Fix the error in the VHDL Code:

Errors:

Error (10344): VHDL expression error at lab7.vhd(125): expression has 19 elements, but must have 18 elements

(port map(opcode=>op_code, uop=>uop_result, clock =>clk, clear=>reset,)

Code:

library ieee;

use ieee.std_logic_1164.all;

library lpm;

use lpm.lpm_components.all;

entity lab7 is

port(AC0, AC1, IR0, IR1, MAR0, MAR1, PC0, PC1: out std_logic_vector (0 to 6);

led1, led2, led3, led4, led5: out std_logic;

clk, reset, pause: in std_logic);

end lab7;

architecture lab7_arch of lab7 is

signal clk2: std_logic;

signal v: std_logic;

signal alu_op: std_logic_vector(0 downto 0);

signal mem_we: std_logic;

signal condition: std_logic;

component exp7_alu is

port (a, b: in std_logic_vector(7 downto 0);

op: in std_logic_vector(0 downto 0);

result: out std_logic_vector(7 downto 0));

end component;

component exp7_useq is

generic (uROM_width: integer := 28; uROM_file: string := "");

port (opcode: in std_logic_vector(3 downto 0);

uop: out std_logic_vector(1 to (uROM_width-9));

enable, clear, clock: in std_logic);

end component;

component decoder is

PORT(clk,reset: in std_logic;

input: IN STD_LOGIC_VECTOR(7 downto 0);

output1, output2: OUT STD_LOGIC_VECTOR (0 to 6));

end component;

signal dr_mux_d, mar_mux_d, mar_mux2_d, ac_mux_d: std_logic_2D(1 downto 0, 7 downto 0); --MUX Signals

signal dr_mux_q, mar_mux_q, mar_mux2_q, ac_mux_q: std_logic_vector(7 downto 0);

signal z_mux_d: std_logic_2D(1 downto 0, 0 downto 0); --Z MUX Signals

signal z_mux_q: std_logic_vector(0 downto 0);

signal pc_q, dr_q, ir_q, mar_q, r_q, alu_q, ac_q, sp_q: std_logic_vector(7 downto 0); --OUTPUT Signals

signal z_q: std_logic_vector(0 downto 0);

--CONTROL Signals

signal dr_mux_sel, mar_mux_sel, mar_mux2_sel, ac_mux_sel, z_mux_sel: std_logic_vector(0 to 0); --MUX Select

signal pc_load, dr_load, ir_load, mar_load, r_load, ac_load, z_load, sp_load: std_logic; --Load

signal pc_inc, sp_inc, sp_dec: std_logic; --Increment/Decrement

signal pc_clr, ir_clr: std_logic; --Clear

signal enable, useq_pause: std_logic; --MICRO-OP

signal uop_result: std_logic_vector(18 downto 0);

signal op_code: std_logic_vector(3 downto 0);

signal ram_output: std_logic_vector(7 downto 0); --RAM Signals

begin

Delay: lpm_counter --Clock Delay

GENERIC MAP(lpm_width=>23)

PORT MAP(clock=>clk, cout=>clk2);

v <= ac_q(7) or ac_q(6) or ac_q(5) or ac_q(4) or ac_q(3) or ac_q(2) or ac_q(1) or ac_q(0); --Signal Values

enable <= clk2;

pc_clr <= uop_result(17) and enable; --PC Signal Values

pc_inc <= uop_result(16) and enable;

pc_load <= ((condition and z_q(0)) or uop_result(15)) and enable;

dr_load <= uop_result(14) and enable; --DR Signal Values

dr_mux_sel(0) <= uop_result(13);

ir_load <= uop_result(5) and enable; --IR Signal Value

mar_load <= uop_result(8) and enable; --MAR Signal Values

mar_mux_sel(0) <= uop_result(7);

mar_mux2_sel(0) <= uop_result(18);

r_load <= uop_result(11) and enable; --R Signal Values

alu_op(0) <= uop_result(10); --ALU Signal Value

ac_load <= uop_result(12) and enable; --AC Signal Values

z_load <= uop_result(4) and enable; --Z Signal Value

sp_load <= uop_result(2) and enable; --SP Signal Values

sp_inc <=uop_result(1) and enable;

sp_dec <= uop_result(0) and enable;

condition <= uop_result(3) and enable; --Condition Signal Value

mem_we <= uop_result(6) and enable; --Memory Write Enable Value

ac_mux_sel(0) <= uop_result(9);

useq_pause <= pause; --MicroSequencer pause Value

op_code <= ir_q(7 downto 4); --Opcode Value

led1 <= mar_load; --L3

led2 <= pc_inc;

led3 <= dr_load; --L5

led4 <= dr_mux_sel(0);

led5 <= ir_load; --L7

UOP: exp7_useq --UROM File

generic map(uROM_width =>27, uROM_file =>"urom.mif")

port map(opcode=>op_code, uop=>uop_result, clock =>clk, clear=>reset,

enable=>enable and not pc_clr);

pcREG: lpm_counter --PC register

generic map(lpm_width => 8)

port map(data=>dr_q, q=>pc_q, sload=>pc_load, sclr=>pc_clr,

aclr=>reset, clock=>clk2, cnt_en=>pc_inc);

genDR: for i in 0 to 7 generate --DR MUX

dr_mux_d(1, i) <= ram_output(i);

dr_mux_d(0, i) <= ac_q(i);

end generate;

drMUX: lpm_mux

generic map (lpm_width => 8, lpm_size=>2, lpm_widths=>1)

port map (result=>dr_mux_q, data=>dr_mux_d, sel=>dr_mux_sel);

drREG: lpm_ff --DR register

generic map(lpm_width => 8)

port map(data=>dr_mux_q, q=>dr_q, aclr=>reset, clock=>clk, enable=>dr_load);

irREG: lpm_ff --IR register

generic map(lpm_width => 8)

port map(data=>dr_q, q=>ir_q, aclr=>reset, clock=>clk, enable=>ir_load);

genMAR: for i in 0 to 7 generate --MAR MUX

mar_mux_d(1, i) <= mar_mux2_q(i);

mar_mux_d(0, i) <= pc_q(i);

end generate;

marMUX: lpm_mux

generic map (lpm_width => 8, lpm_size=>2, lpm_widths=>1)

port map (result=>mar_mux_q, data=>mar_mux_d, sel=>mar_mux_sel);

genMAR2: for i in 0 to 7 generate --MAR MUX 2

mar_mux2_d(1, i) <= dr_q(i);

mar_mux2_d(0, i) <= sp_q(i);

end generate;

marMUX2: lpm_mux

generic map (lpm_width => 8, lpm_size=>2, lpm_widths=>1)

port map (result=>mar_mux2_q, data=>mar_mux2_d, sel=>mar_mux2_sel);

marREG: lpm_ff --MAR register

generic map(lpm_width=>8)

port map(data=>mar_mux_q, q=>mar_q, aclr=>reset, clock=>clk, enable=>mar_load);

rREG: lpm_ff --R register

generic map(lpm_width => 8)

port map(data=>dr_q, q=>r_q, aclr=>reset, clock=>clk, enable=>r_load);

ALU: exp7_alu --ALU

port map(a => r_q, b => ac_q, op => alu_op, result => alu_q);

genAC: for i in 0 to 7 generate --AC MUX

ac_mux_d(1, i) <= dr_q(i);

ac_mux_d(0, i) <= alu_q(i);

end generate;

acMUX: lpm_mux

generic map (lpm_width => 8, lpm_size=>2, lpm_widths=>1)

port map (result=>ac_mux_q, data=>ac_mux_d, sel=>ac_mux_sel);

acREG: lpm_ff --AC register

generic map(lpm_width => 8)

port map(data=>ac_mux_q, q=>ac_q, aclr=>reset, clock=>clk, enable=>ac_load);

z_mux_d(1,0) <= v; --Z MUX

z_mux_d(0,0) <= not v;

z_mux_sel(0) <= ir_q(0);

zMUX: lpm_mux

generic map (lpm_width => 1, lpm_size=>2, lpm_widths=>1)

port map (result=>z_mux_q, data=>z_mux_d, sel=>z_mux_sel);

zREG: lpm_ff --Z register

generic map(lpm_width => 1)

port map(data=>z_mux_q, q=>z_q, aclr=>reset, clock=>clk, enable=>z_load);

spREG: lpm_counter --SP register

generic map(lpm_width => 8)

port map(data=>dr_q, q=>sp_q, sload=>sp_load,

aclr=>reset, clock=>clk2, cnt_en=>sp_inc or sp_dec, updown=>sp_inc);

RAM: lpm_ram_dq --RAM

generic map(lpm_width=>8, lpm_widthad=>8, lpm_file=>"exp7_ram1_4.mif")

port map(data=>dr_q, address=>mar_q, we=> mem_we, q=>ram_output, inclock=>clk, outclock=>clk);

ACDisp: decoder port map(input=>ac_q, output1=>AC0, output2=>AC1, clk=>clk, reset=>reset);

PCDisp: decoder port map(input=>pc_q, output1=>PC0, output2=>PC1, clk=>clk, reset=>reset);

MARDisp: decoder port map(input=>mar_q, output1=>MAR0, output2=>MAR1, clk=>clk, reset=>reset);

SPDisp: decoder port map(input=>sp_q, output1=>IR0, output2=>IR1, clk=>clk, reset=>reset);

end lab7_arch;