For a CMOS inverter, assume that the load capacitance is C = 120 fF, the dynamic power dissipated in the inverter is PD = 78.40 W and VDD = 3.3V. The inverter is cycled through the low and high voltage levels at an average rate of F MHz (a) Calculate the value of F? (1 point) (b) For a chip that contains the equivalent of 350,000 inverters, calculate the total dynamic power dissipated if 45 percent of the gates change values at any given time. (1 point)