For a CPU with 16 bit addresses, paged virtual memory is used, there is 4 KB of real memory in frames of 256 bytes each. It takes 10 millisecs (10-2 sec) to read or write a page to the swap flash, and it takes 2 microsecs (2 x 10-6) to read or write main memory (ignore the time to translate in page table), the current page table contents are:

Page Entry Memory Frame Valid Dirty Clock time page loaded

0 2 1 1 120

1 2 0 0 108

2 3 1 1 100

3 1 0 1 112 (a) How large (bytes) is total, addressable (logical) memory? (b) How large is a memory page? (c) How many entries (maximum) is the page table? (d) If the hit rate is 98%, what is the average memory access time (with VM)? (e) One of the page replacement algorithms (policy) is FIFO (e.1) Briefly (few words), which page would be replaced? (e.2) when does page replacement happen (in this VM)? (f) For the following logical (data pointer) addresses, please give the corresponding physical addresses (if possible): (f.1) 0 ->__________ (f.2) 110 Hex ->___________________ (f.3) 205 Hex ->____________________ (g) For the following physical addresses, please give the corresponding logical addresses (if possible): (g.1) 301 ->__________ (h) How large (bytes) is total, physical memory? (i) We wish to decrease the average memory access time. How much would each of the following help (how much faster)? (i.1) Change reading swap disk pages to take 5 ms. (i.2) Double available real memory so hit rate is twice as good. (i.3) Put page table in real memory. (j) For page entry 3, the dirty bit is 1. How would that be used? (k) Page 0 and 1 both have an frame entry of 2. Is this a problem, can this be possible?