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For a direct mapped cache design with 3 2 - bit address, the address is divided as follows: - bits 0 - 3 are used
For a direct mapped cache design with bit address, the address is divided as follows:
bits are used for the offset
bits are used for the index
bits are used for the tag
If the CPU references the addresses and in which line and which byte these can be found?
Select one:
a line byte and byte
b line the same byte
c line bye and byte
d line the same byte
e line bye and byte
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