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For a direct mapped cache design with 3 2 - bit address, the address is divided as follows: - bits 0 - 3 are used

For a direct mapped cache design with 32-bit address, the address is divided as follows:
- bits 0-3 are used for the offset
- bits 4-9 are used for the index
- bits 10-31 are used for the tag
If the CPU references the addresses 100 and 101, in which line and which byte these can be found?
Select one:
a. line 4, bye 5 and byte 6
b. line 5, byte 4 and byte 6
c. line 6, the same byte
d. line 6, bye 4 and byte 5
e. line 5, the same byte

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