Question
For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache. Tag Index Offset 31-12 11-6
For a direct-mapped cache design with a 32-bit address, the following bits of address are used to access the cache.
| Tag | Index | Offset |
| 31-12 | 11-6 | 5-0 |
a, what is the cache block size (in words)?
b, how many entries does this cache have?
c, What is the ratio between total bits required for such a cache implementation over the data storage bits?
Step by Step Solution
There are 3 Steps involved in it
Step: 1
Get Instant Access to Expert-Tailored Solutions
See step-by-step solutions with expert insights and AI powered tools for academic success
Step: 2
Step: 3
Ace Your Homework with AI
Get the answers you need in no time with our AI-driven, step-by-step assistance
Get Started
Database Management An Organizational Perspective
Authors: Richard T. Watson
1st Edition
0471305340, 978-0471305347
