For a virtual to physical address translation, Xv6 uses a 4KB page directory table which contains 1024 entries of 32bit data structure. Select one incorrect statement regarding this page directory table. The lower 12 bits of each 32bit entry in this page directory table holds the byte offset value within the 4 KB physical frame. The upper 20 bits of each 32bit entry in this page directory table holds the physical address of the corresponding page table. For context switching, Xv6 scheduler needs to set cr3 register to the base address of the page directory table. The security and the protection validation of each memory reference is accomplished using this page directory table. Question 5 4 pts Consider the following C macro definition PDX in mmu.h \[ \text { \#define PTE_ADDR(pte) ((uin } t)(p t e) \& \sim 0 x F F F) \] What will be the value of PTE_ADDR ( OxACF1E1D )? 0xACF1000 OxE1D OxF1E1D