For both parts of the problem we examine the dependencies of the following code sequence: lw $2, 0($3) addi $4, $2,50 add $3, $2, $4 lw $2,4($3) add $4, $3, $4 Assumption we are using the classic 5-stage pipeline and that the registers can Write/Read in the same clock cycle. S.1 Draw a multi-cycle timing diagram (similar to Fig 4.53 and slide 81) to show the execution through the pipeline. Show stalls forwarding has not been implemented. where appropriate. For this case S.2 Draw a multi-cycle timing diagram (similar to Fig 4.53 and slide 81) to show the execution through the pipeline. Show stall appropriate. For this case full forwarding is implemented. s and any forwarding where