For questions 11-14. consider the following code: ADDI S51, S. -1 ANDI S-2, S2. 10 BEQ S1, S2, L1 LW $64.0(51) LI: SW 2.4(Ss1) 11. All instructions of the above program are using the immediate addressing mode. A True B. False 12. If the program is executed on a single-cycle MIPS processor, then the CPI of the program will be: A1 B2 C4 DS 13. If the program is executed on a multi-cycle MIPS processor, then the CPI of the program will be: A! B. 2.4 C. 4.2 D. None of the above. 14. If the program is executed on a pipelined MIPS processor, then control hazard could occur A. True B. False 15. Consider executing the following code on the pipelined processor: ADDIS2, S3, 1 ADD 55, 53, 51 SUB SA, S1, S2 SW $56, 4(550) At the end of the fifth cycle of execution, which registers are being read and which will be written: A $s3 is being read, and Ss2 will be written B. Only Ss3 is being read, and no register will be written. C. $s3 and Ss0 are being read, no register will be written D. Ss1,543, S1, S2, and S50 are being read, and S-2, S4, S55 and Ss6 will be written. E. None of the above