For the five stage MIPS pipeline with full bypass and stall logic, explain the hazard in each of the following sequences (if any), and how to resolve it.

1

lw     $t1   42($t1) sub    $t4   $t1    $t2 add    $t2   $t3    $t3

2

lw     $t1    42($t1) sub    $t4    $t2    $t3 add    $t4    $t2    $t3

3

add    $t1    $t2    $t3 add    $t1    $t1    $t1 beq    $t1    $t4    .L1

4

lw     $t1    42($t1) $t3    $t2    $t3 sub    $t4    $t1    $t3