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For the flip-flop circuit shown in the figure, the set-up (ts) and hold (th) times for the flip-flop is 0.5 ns and 0.05 ns,
For the flip-flop circuit shown in the figure, the set-up (ts) and hold (th) times for the flip-flop is 0.5 ns and 0.05 ns, respectively, and its propagation delay (tCQ) is 0.8 ns =
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Digital Systems Design Using Verilog
Authors: Charles Roth, Lizy K. John, Byeong Kil Lee
1st edition
1285051076, 978-1285051079
