For the following activities, make sure to open a new project and save it to the same folder

where you have your Lab $2$ so that the new design can be accessed by Lab $2$ design. So when

saving your new project, choose the destination to Lab $2$ folder that you have already. The

software will warn you that, the Folder that you are choosing has already a design and will

recommend you to put into another folder, but you will click No$.$

$1)$ Write VHDL code for a full adder circuit $($ refer to Lab $1$ and also Fig $1$ here$)$ for the

design of full adder$).$ Remember, the project name and the VHDL entity name need

to be the same.

$2)$ Simulate the circuit for functional behavior

$3)$ Create a symbol for this circuit

$4)$ Open the $.$qpf file of Lab $2$ design and replace the full adder symbol that you used in Lab

$2$ by this newly created symbol. Compile the design and fix any errors.

$5)$ Simulate the $8-$bit adder as being done in Lab $2.$

Fig $1$: Full Adder schematic diagram