For the following clocked sequential circuit with one input (X) and one output (Z): a) Drive a state table and draw a state diagram for a sequence detector that outputs a 'I' when it detects the final bit in the serial data stream 111, for Mealy Machine. b) Redesign this circuit by replacing the QI flip-flop (i.e. the D flip-flop holding Q1 state) with a JK flipflop, and the Q2 flip-flop with a T flip-flop. Only show the excitation equations (or state equations) for J1, K1, and T2. Do CLK Q1 D Do Q2