For the following exercises, assume that the ALU can output an equals signal, which is high/on/one when its two inputs are equal.

Label all 5 stages in the following diagrams to indicate which part of the hardware is used for each stage (Instruction Fetch, Decode/Register Read, Execute, Memory, Register Write)

Label the unlabelled wires in the diagram above, describing what data is on each line. For example, one of the outputs of the registers block could be R[rs]. Here are the words you should put in:

nextPC, curPC, branch offset, dataIn, dataAddr, dataOut, R[rs], R[rt]

Add control signals and missing elements (such as multiplexers) to the diagram below so that the datapath can execute the following instructions: add, lui, sw, bne

(Note: you must label the control signals lines: such as nPC_Sel)

For the following exercises, assume that the ALU can output an "equals" signal, which is high/on/one when its two inputs are equal 1. Label all 5 stages in the following diagrams to indicate which part of the hardware is used for each stage (Instruction Fetch, Decode/Register Read, Execute, Memory, Register Write) 2. Label the unlabelled wires in the diagram above, describing what data is on each line. For example, one of the outputs of the registers blockcould be Rlrsl. Here are the words you should put in: next PC, curPC, branch offset, dataIn, dataAddr, dataout, RIrsl, RIrt] 3. Add control signals and missing elements (such as multiplexers) to the diagram below so that the datapath can execute the following instructions: add, lui, aw, boe (Note: you must label the control signals lines: such as nPC Sel) 6 9 rs imm opcode/ funct Control