For the following given verilog code provide the circuit diagram in terms of specified gates. Also provide the boolean expressions as per the code without simplifications

module example13 (A, B, C, D, F1, F2);
//input and outputs declarations

input  A, B, C, D;
output F1, F2;

// Internal wires declarations
wire T1, T2, T3, T4;
wire W1, W2, W3;

// Inverters for input signals
not NOT_1  (W1, A);
not NOT_2  (W2, B);
not NOT_3  (W3, D);

//Intermediate stage for te gates
and AND2_1 (T1, W2, C);
and AND2_2 (T2, W1, B);
or  OR2_1  (T3, T1, A);
xor XOR2_1 (T4, T2, D);

// Output signal stage
or  OR2_2  (F1, T3, T4);
or  OR2_3  (F2, T2, W3);

endmodule