For the following questions answers should be no longer than one or two sentences:

1. A processor executes every ALU instruction in 1 cycle, load and store instructions in 2 cycles, and branches in 3 cycles. If 45% of instructions are ALU instructions, 30% are load/store instructions, and all remaining instructions are branches, what is the resulting CPI (cycles per instruction) of that machine? What is the resulting speedup if the latency of branches is reduced by an architectural change to one cycle? 2. An application is ported to a 16-core multiprocessor. 75% of the application can be parallelized. What is the best expectable speedup compared to single-core performance? 3. Consider a machine where retrieving a memory word from a cache takes 2 cycles. If a miss occurs (data not found in the cache) the word needs to be brought in from the memory which takes 100 cycles. If on 1000 memory accesses there are 120 misses, what is the average memory access time?