For the given clock and D signals, what is the resulting output at Q? For the D register, using the same clock and D signals, what is the resulting outputs at -QL and QR? You can use the dashed boxes shown under the given signals for your answers, though you should provide a written explanation, too.

Suppose that A3=0,A2=0,A1=1,A0=1, and "count enable"=1. What values will the flip-flops store after the next rising edge of the clock?

CLK 61% 6:15 PM Mon Feb 18 Meme Count enable K Output Clock Figure 2-10 4-bit synchronous binary