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For the MIPS architecture with a five stage pipeline as given in the text for the code below ( in order issue and execution )

For the MIPS architecture with a five stage pipeline as given in the text for the code below (in
order issue and execution).
LW R6,30(R2)
LW R4,30(R6)
AND R2,R4,R6
SW R2,30(R6)
ADD R6, R2,R8
SW R8,30(R2)
(i) Identify the types of data hazards in executing the following code. (Clearly showing in
which instruction and why).
(ii) If there are no data forwarding units and hazards are handled by stalls show cycle by cycle
execution sequence in the pipeline for the code.
(iii) If the data forwarding units are available show cycle by cycle execution sequence in the
pipeline for the code with the necessary data forwarding or stalls as applicable. Show the
necessary forwarding paths in the sequence and stalls if any required in the sequence.

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