For this problem, assume gate delays of 1ns, bus propagation delays of 2ns, latch propagation delays of 3ns, and no other delays. Also assume unlimited gate fan-in and fan-out. You should also assume that latch propagation delays include setup, hold, and minimum pulse width times, as shown in Figure 4.11.

a. Consider the control unit shown in Figure 4.12 How long does it take for the control signals to become valid at the output of the control unit from the time of the risiing edge of the T control step signal? Assume that the decoded opcode signals are valid at the rising edge of the clock.