For this problem, assume that individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
300 ps	250 ps	200 ps	300 ps	150 ps

For our workload, assume that the instructions executed by the processor are broken down as follows:

ALU / Logic	Jump	Branch	Load	Store
35%	10%	20%	20%	15%

a. (1 pt) What is the clock-cycle time for (1) a pipelined and (2) a non-pipelined processor?

b. (1 pt) What is the total latency of an lw instruction in (1) a pipelined and (2) a non-pipelined processor?