From the truth table, write the verilog code.

13 12 11 11 Q1 QO 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 1 1 1 0 0 0 1 Q1 = 13 +12 Q2 = 13 + 11 4:2 Encoder BLOCK CH always 1 reg (1:0) 13:01 01:01 13:01 01101 alwayse() // Looks for a change on any defined input. 5 begin Q[1] . 1[3] | 1(2); 31/ Add your code here 6 7 8 end