Fundamentals of Digital Logic Spring 2020 (Online) Assignment#61 Chapter 5) 1- For three types of Flip-Flops, D, T and J-K Flip Flop, find the outputs QD, Qjk and Qt when applying the clock pulses and the inputs in the following timing diagram. Note: Flip flops in this question are +ve edge triggered. 2. For a Basic SR latch and a Gated SR latch DODO D.DE Basic SR atch Gated SR latch If the following input signals are applied to S, R and clk nodes, find out the output signals generated in Qa. Qu. Q and Q'. Assume that S and Rinputs for both the basic SR latch and Gated SR latch are receiving the same input signals. clk 3. Design a 4-bit shift left register using I flip-flop. Draw the complete block diagram with all wires, inputs and outputs clearly illustrated