GCD circuit calculates the greatest common divisor (GCD) of two binary positive 4-bit numbers. The operand registers, p and q, are initialized with the

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GCD circuit calculates the greatest common divisor (GCD) of two binary positive 4-bit numbers. The operand registers, p and q, are initialized with the activation of a start signal, which commences the computation process. On completion of the computation, an output g and a signal done are asserted to indicate that the data on the GCD outputs are valid. The corresponding ASM-Chart and the algorithm are given in Figure Q8(a) and Figure Q8(b) respectively. g q-p SO S1 q reset start -q0 p = q Figure Q8(a) 0 p (a) (b) (c) Initialize: p = p0; q = q0; while (p #q) { if (p > q) then p=p-q; else 9=9-p; end if g= p; Figure Q8(b) Specify the type of the Finite State Machine (FSM) - Moore or Mealy. Create the input-output block diagram (iobd), showing the overall system. Construct the functional block diagram (fbd) of the control unit, clearly labelling all signals.